14 Juin 1998 
Nice, France 
Shanxi, China 
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I am Ran GUO.
I'm an embedded systems engineer.
I'm now a Ph.D. Student in France.
Hello!
Wellcome to my personnal page!
My name is Ran Guo. Nice to meet you all!
I look forward to telling you more about my life and work experiences.
2021 - Present
Large-scale three-dimentional particle tracking velocimetry for indoor inflow study.
R. Guo, E. Dekneuvel, G. Jacquemod, and P. H. Biwole, “From SysML Application Model to Executable OpenCL Code: A System-Level Design Approach” 13th Mediterranean Conference on Embedded Computing (MECO), Budva, Montenegro: IEEE, Juin. 2024, pp. 1-6, doi:10.1109/MECO62516.2024.10577799. (oral presentation).
R. Guo, E. Dekneuvel, G. Jacquemod and P. Biwole, “A system-level description of a particle tracking velocimetry system for indoor air quality study”, Science Talks, Elsevier, Vol. 5, Article ID 100099, 6 pages, 2023, doi: 10.1016/j.sctalk.2022.100099.
R. Guo, E. Dekneuvel, G. Jacquemod, and P. H. Biwole, “Real-time PTV system implementation on multi-SoC architecture accelerated by OpenCL,” in 2024 International Conference on Artificial Intelligence, Computer, Data Sciences and Applications (ACDSA), Victoria, Seychelles: IEEE, Feb. 2024, pp. 1–6. doi: 10.1109/ACDSA59508.2024.10467455. (oral presentation).
R. Guo, E. Dekneuvel, G. Jacquemod and P. Biwole, A system-level description of a particle tracking velocimetry system for air quality study, MeSSAC, Jinan, China, 2022. (oral presentation).
J. Li, J. Zhang, Y. Jiang, C. Ren, R. Guo, Y. Ma and Y. Qin, "A Flexible and Miniaturized Chest Patch for Real-time PPG/ECG/Bio-Z Monitoring," 2022 44th Annual International Conference of the IEEE Engineering in Medicine & Biology Society (EMBC), Glasgow, Scotland, United Kingdom, 2022, pp. 4312-4315, doi: 10.1109/EMBC48229.2022.9872005.
C. Chen, I. Kim, Y. Jiang, J. Zhang, R. Guo, Y. Ma, P. D'Angelo and Y.Qin, "A 17.7µW CDS-CTIA for Wireless-powered Wearable Electrochemical Sweat Sensors," 2022 44th Annual International Conference of the IEEE Engineering in Medicine & Biology Society (EMBC), Glasgow, Scotland, United Kingdom, 2022, pp. 4622-4625, doi: 10.1109/EMBC48229.2022.9871740.
J. Zhang, J. Li, Y. Jiang, K. Wang, R. Guo, Y. Ma and Y. Qin, "A Hardware-based Lightweight ANN for Real-time Wearable Blood Pressure Estimation," 2022 44th Annual International Conference of the IEEE Engineering in Medicine & Biology Society (EMBC), Glasgow, Scotland, United Kingdom, 2022, pp. 4295-4298, doi: 10.1109/EMBC48229.2022.9871215.
R. Guo, E. Dekneuvel, G. Jacquemod & P. Biwole, “Large-scale three-dimensional particle tracking velocimetry for indoor inflow study”, Workshop CSC-Polytech, Paris, 2022. (oral presentation).
2019 - 2021
C++, Java, VHDL, Analog signal processing, FPGA, Embedded Linux, Digital automatic, Embedded system conception, SoCP conception, UML, SystemC, RTOS, Robotic, Digital verification (UVM verification), High level synthesis, Autonomous driving.
2016 - 2020
C language, Digital image processing, Microcomputer principle and system design, Assembly experiment of computer system, Random signal analysis, Fundamental of analog electonic technology, Digital circuit and logic design, The principle of automatic control.
The main visiting subjects include: information theory applications, renewable electrical energy, nanomaterial science, etc. It lasts for 18 days, and finally passes the presentation assessment and obtains a training certificate.
Febrary - August 2021
Rapid prototype development for 3D PTV (three-dimentional particle tracking velocimetry) system using LabVIEW.
May - August 2020
FMU files encapsulated and parsed using the FMI standard.
SSH connection to the VM and transfer of files by generating a QT interface to launch running Matlab files using QT calls.
Intership Report
Due to confidentiality reasons, the internship report will not be made public. Please contact me for more information.
SoC, FPGA, OpenCL, real-time system, parallel optimization
The system realizes high-precision tracking and velocimetry of particles through advanced algorithms and hardware architecture. System-level modeling is used to combine the SoC architecture with particle tracking algorithms to build a platform with multiple camera inputs and realize real-time data processing. Optimizing the application of OpenCL parallel technology, the system finally achieves a real-time processing speed of 8 frames per second (2048x2048 pixels) on Cyclone V FPGA, which meets the monitoring environment of indoor airflow of 3-6 m/s.
System level modeling using UML, SysML, RPN, etc.
Rapid prototyping with LabVIEW.
Implement basic algorithms including particle detection, trajectory tracking, spatial matching and 3D reconstruction using C and C++. Realize real-time 3D display using OpenCV graphics library.
Using OpenCL for task pipeline acceleration and more, particle detection can be achieved at up to 48 frames per second on Arria10 FPGAs.
Custom Linux development, driver development, device tree generation, configuration of appropriate OS for SoC board hardcore systems.
Click here to see Youtube video presentation: Youtube video 1,
Youtube video 2
C++, OpenCV
Combining C++ and OpenCV libraries, I developed a multi-camera calibration system that can run on multiple SoC platforms, enabling precise geometric alignment of image data captured by multiple cameras in 3D space for accurate 3D reconstruction or scene analysis. The system enables accurate calibration and synchronisation of multiple industrial cameras and is capable of handling real-time data streams from multiple cameras to ensure high performance and scalability. Using a 5x7 checkerboard calibration board, the average speed of calibration can reach 0.0223 seconds per frame.
Click here to see Youtube video presentation: Youtube video
Contact me for source code and more information.
Linux, ZedBoard, Device tree, Bootloader
Description ...
Contact me for more information.
Java, Socket
Description ...
Click here to see Youtube video presentation : Youtube video
Contact me for source code and more information.
C/C++, Zedboard, FPGA, CNN, Vivado HLS
Full development of a Convolutional Neural Network (CNN) accelerated on a CPU / FPGA system using High Level Synthesis (HLS).
Handwritten digit recognition from 0 to 9 is achieved by developing accelerated Convolutional Neural Network (CNN) on Zedboard FPGA. The project used the Keras framework to train the resultant weight files, and implemented the Lenet5 architecture based on C, including convolution, pooling, etc. The test used 10,000 images with a success rate of 97.9%. In the hardware part, the high-level synthesis technique HLS is used to optimize the execution time, and the Vivado HLS tool is used to convert the C code into hardware description language. After a series of pipeline optimization, the hardware acceleration is 2.11 times faster than CPU operation.
Zynq-7000 SoC (ARM dual core Cortex-A9 / Xilinx FPGA).
Click here to see Youtube video presentation : Youtube video
Click here to find source code : github Link
Click here to see project report : Report
C++, MySQL, Gtkmm
Designed and developed an escape room game in Linux environment using C++, skillfully integrating the gtkmm library for graphical interface functionality. The game uses MySQL for user data storage and management to ensure data reliability and security.
Click here to see Youtube video presentation : Youtube video.
Click here to find source code : project Link
Arduino
Completed the design and construction of the internal structure of the surfboard, using the microcontroller VESC as the core, through the vesc tool to control the motor for the operation of the surfboard.
Familiarize with the arduino for the remote control and lights.
Assemble a temperature sensor to control the pump to cool down the microcontroller with water flow.
Configuration of power supply and safety locks.
Click here to see project report : Report
C++, QT
Description ...
Click here to see project report : Report
Click here to find source code : github Link
C++, QT
An interactive image processing application was developed using C++ in a QT environment, using multithreading techniques and SIMD instructions to optimize the system runtime and significantly improve the performance and responsiveness of image processing.
Key words: Filter FIR; Convolution; SIMD; Threads
Click here to see project report : Report
Click here to find source code : github Link
DE10 standard development board (Intel)
Cyclone 10 GX FPGA Development Kit (Intel)
Arria 10 SoC Development Kit (Intel)
Zedboard (Xilinx)
NI PCIe-1477 (National Instruments)
Odroid-Xu4
Arduino UNO
Esp 32 piko kit
My Diaries
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Phone (fr): (+33) 658035627
Phone (cn): (+86) 15291686810
guor1998@163.com
guor1998@gmail.com
15291686810
06200 Nice, France
Because I answer the phone infrequently, please reach me via email, voicemail or wechat.